Doctor of Philosophy

dissertationPortable electronic devices will be limited to available energy of existing battery chemistries for the foreseeable future. However, system-on-chips (SoCs) used in these devices are under a demand to offer more functionality and increased battery life. A difficult problem in SoC design is providing energy-efficient communication between its components while maintaining the required performance. This dissertation introduces a novel energy-efficient network-on-chip (NoC) communication architecture. A NoC is used within complex SoCs due it its superior performance, energy usage, modularity, and scalability over traditional bus and point-to-point methods of connecting SoC components. This is the first academic research that combines asynchronous NoC circuits, a focus on energy-efficient design, and a software framework to customize a NoC for a particular SoC. Its key contribution is demonstrating that a simple, asynchronous NoC concept is a good match for low-power devices, and is a fruitful area for additional investigation. The proposed NoC is energy-efficient in several ways: simple switch and arbitration logic, low port radix, latch-based router buffering, a topology with the minimum number of 3-port routers, and the asynchronous advantages of zero dynamic power consumption while idle and the lack of a clock tree. The tool framework developed for this work uses novel methods to optimize the topology and router oorplan based on simulated annealing and force-directed movement. It studies link pipelining techniques that yield improved throughput in an energy-efficient manner. A simulator is automatically generated for each customized NoC, and its traffic generators use a self-similar message distribution, as opposed to Poisson, to better match application behavior. Compared to a conventional synchronous NoC, this design is superior by achieving comparable message latency with half the energy

Network simplicity for latency insensitive cores

Journal ArticleIn this paper we examine a latency insensitive net- work composed of very fast and simple circuits that connects SoC cores that are also latency insensitive, de-synchronized, or asynchronous. These types of cores provide native flow control that is compatible with this network, thus reducing adapter overhead and buffering needs by applying backpressure directly to the sending core. We show that under realistic traffic patterns our sample network meets performance requirements and uses less power compared to a similar design. This concept of a simplified network, along with latency insensitive cores lends itself well to meeting the needs of low-power interconnect components in future design processes

Comparing energy and latency of asynchronous and synchronous NoCs for embedded SoCs

Journal ArticlePower consumption of on-chip interconnects is a primary concern for many embedded system-on-chip (SoC) applications. In this paper, we compare energy and performance characteristics of asynchronous (clockless) and synchronous network on-chip implementations, optimized for a number of SoC designs. We adapted the COSI-2.0 framework with ORION 2.0 router and wire models for synchronous network generation. Our own tool, ANetGen, specifies the asynchronous network by determining the topology with simulated-annealing and router locations with force-directed placement. It uses energy and delay models from our 65 nm bundled-data router design. SystemC simulations varied traffic burstiness using the self-similar b-model. Results show that the asynchronous network provided lower median and maximum message latency, especially under bursty traffic, and used far less router energy with a slight overhead for the interrouter wires

Power reduction through physical placement of asynchronous routers

Journal ArticleOur work reduces power consumption by minimizing wirelength and hop-count of an asynchronous NoC using simulated annealing and force-directed algorithms. Asynchronous NoCs (aNoCs) can provide important benefits over clocked NoCs. However, there is little published research on generating a custom, optimized aNoC for a fixedfunction, power-constrained system-on-chip (SoC). Such tools must consider physical SoC properties and especially NoC link delay and power. Our research is motivated by this need, and the mantra that ?transistors are fast, wires are slow and power-hungry,? due to process scaling differences between transistors and global wires

Design and stratification of PASS : a new panel study for research on long term unemployment

"The paper introduces the general design features and particularities of a new largescale panel study for research on recipients of benefits for the long-term unemployed (the so called Unemployment Benefit II) in Germany that combines a sample of 6000 recipient households with an equally large sample of the general population. Particular focus is on the sampling procedure for the general population, where a commercial database was used to draw a sample stratified by status." (Author's abstract, IAB-Doku) ((en))IAB-Haushaltspanel - Konzeption, empirische Sozialforschung, Erhebungsmethode, Stichprobe, Langzeitarbeitslosigkeit

Unbiased Cosmological Parameter Estimation from Emission Line Surveys with Interlopers

The galaxy catalogs generated from low-resolution emission line surveys often contain both foreground and background interlopers due to line misidentification, which can bias the cosmological parameter estimation. In this paper, we present a method for correcting the interloper bias by using the joint-analysis of auto- and cross-power spectra of the main and the interloper samples. In particular, we can measure the interloper fractions from the cross-correlation between the interlopers and survey galaxies, because the true cross-correlation must be negligibly small. The estimated interloper fractions, in turn, remove the interloper bias in the cosmological parameter estimation. For example, in the Hobby-Eberly Telescope Dark Energy Experiment (HETDEX) low-redshift ($z<0.5$) [O II] $\lambda3727${\AA} emitters contaminate high-redshift ($1.9<z<3.5$) Lyman-$\alpha$ line emitters. We demonstrate that the joint-analysis method yields a high signal-to-noise ratio measurement of the interloper fractions while only marginally increasing the uncertainties in the cosmological parameters relative to the case without interlopers. We also show the same is true for the high-latitude spectroscopic survey of Wide-Field Infrared Survey Telescope (WFIRST) mission where contamination occurs between the Balmer-$\alpha$ line emitters at lower redshifts ($1.1<z<1.9$) and Oxygen ([O III] $\lambda5007${\AA}) line emitters at higher redshifts ($1.7<z<2.8$).Comment: 36 pages, 26 figure

Codebook and documentation of the panel study 'Labour Market and Social Security' (PASS) : vol. 1: Introduction and overview, wave 1 (2006/2007)

"The panel study 'Labour Market and Social Security' (PASS), established by the Institute for Employment Research (IAB), is a new dataset for labour market, welfare state and poverty research in Germany, creating a new empirical basis for the scientific community and political consulting. This Datenreport provides an overview of the first survey wave, for which 18,954 persons were interviewed in 12,794 households between December 2006 and July 2007. The study is carried out as part of the IAB's research into the German Social Code Book II (SGB II). The IAB is charged by law with studying the effects of benefits under SGB II for integration into the labour market and subsistence benefits. However, due to the complex sample design, it also enables researchers to answer questions far beyond these issues. Five core questions influenced the development of the new study, which are detailed in Achatz et al. (2007): 1. What options exist to regain independence from Unemployment Benefit II? 2. In which ways does the social situation of a household change when it receives benefits? 3. How do persons concerned cope with their situation? Will attitudes of the respondents that are constitutive for their actions change over time? 4. In which form do contacts between benefit recipients and institutions providing basic social security actually take place? What are the institutional procedures applied in practice? 5. Which employment career patterns or household dynamics lead to receipt of Unemployment Benefit II? The following brief overview describes the motivation for carrying out the survey, its contents and the study design." (text excerpt, IAB-Doku) ((en)) Additional Information Questionnaires of the first wave. Here you can find the German version. Further information about the panel study "Labour Market and Social Security"IAB-Haushaltspanel, Datengewinnung, Erhebungsmethode, Stichprobe, Panel - Methode, Datenaufbereitung

Codebook and Documentation of the Panel Study ‘Labour Market and Social Security’ (PASS) : Datenreport Wave 3

"This wave-specific Datenreport aims to document the wave-related aspects of the study4. Following a short overview of the innovations and characteristics of the third wave (Chapter 1.3.), the key figures on samples and response rates of the third wave are reported (Chapter 2). Moreover, the steps of data preparation and the decisions made as part of this process are described (Chapter 5) and an overview of the variables generated is presented (Chapter 4). Additionally, the weighing procedure is presented (Chapter 6). The separate table reports list the frequencies of all variables included in the scientific use file that were recorded in wave 3, divided into their respective datasets (Volume II to Volume V)." (Author's abstract, IAB-Doku) ((en)) Additional Information Table report II table report III table report IV table report V Questionaires third wave working tools further information german version of this "Datenreport"IAB-Haushaltspanel, Datenaufbereitung, Datenorganisation, Datenzugang, Datenqualität, Datensatzbeschreibung, Erhebungsmethode, Stichprobe, personenbezogene Daten, private Haushalte, Alterssicherung

Entwicklung eines Tests zur Lernverlaufsdiagnostik mit schwierigkeitsgenerierenden Merkmalen. Ein Beispiel für die Diagnose grundlegender arithmetischer Fertigkeiten in der Grundschule

This study investigates difficulty-generating item characteristics (DGICs) in the context of basic arithmetic operations for numbers up to 100 to illustrate their use in item-generating systems for learning progress monitoring (LPM). The fundament of the item-generating system is based on three theory-based DGICs: arithmetic operation, the necessity of crossing 10, and the number of second-term digits. The Rasch model (RM) and the linear logistic test model (LLTM) were used to estimate and predict the DGICs. The results indicate that under the LLTM approach all of the three hypothesized DGICs were significant predictors of item difficulty. Furthermore, the DGICs explain with 20% a solid part of the variance of the RM’s item parameters. The identification and verification of the DGICs under the LLTM approach provide important insights into how to address the challenges in the development of future LPM tests in mathematics. (DIPF/Orig.)Diese Studie untersucht den Einfluss schwierigkeitsgenerierender Merkmale für die Gestaltung von Items zur Lernverlaufsdiagnostik arithmetischer Basiskompetenzen im Zahlenraum bis 100. Das System zur Itemkonstruktion basiert dabei auf drei theoriegeleiteten schwierigkeitsgenerierenden Merkmalen: der verwendeten arithmetischen Operation, der Notwendigkeit des Zehnerübergangs, und der Stellenanzahl des zweiten Terms. Zur Schätzung und Vorhersage der Itemparameter wurden das Rasch-Modell (RM) und das linear-logistische Testmodell (LLTM) verwendet. Die Ergebnisse des LLTM-Ansatzes deuten darauf hin, dass alle drei vermuteten schwierigkeitsgenerierenden Merkmale signifikante Prädiktoren für die Itemschwierigkeit sind. Basierend auf den drei schwierigkeitsgenerierenden Merkmalen konnten 20% der Varianz der Itemschwierigkeitsparameter des RM erklärt werden. Diese Studie verdeutlicht, dass die Identifikation und Prüfung schwierigkeitsgenerierender Merkmale wichtige Erkenntnisse liefern, wie Herausforderungen bei der Entwicklung zukünftiger Tests zur Lernverlaufsdiagnostik in Mathematik berücksichtigt werden können. (DIPF/Orig.